1. Field of the Invention
The present invention relates to a circuit arrangement for receiving binary signals serially appearing on a plurality of signal receiving lines and for processing these binary signals in the form of parallel signals respectively encompassing a prescribed plurality of bits and/or for the transmission of serially appearing binary signals by way of individual signal output lines after a previously occurring processing of parallel signals respectively encompassing the aforementioned plurality of bits in, or, respectively, from a processing device containing a microcomputer or a microprocessor, the processing device being connected at its input and/or output to the signal receiving or, respectively, signal output lines via signal receiving or, respectively, signal transmission devices.
2. Description of the Prior Art
The microcomputers or microprocessors currently used in processing devices are designed such that they are capable of processing binary signals in the respective form of parallel signals. When a serial data stream is to be received or output, separate interface modules are employed between the corresponding receiving lines or, respectively, transmission lines and the respective microcomputer or microprocessor. Such an interface module is, for example, a universal synchronous asynchronous transmitter/receiver module which is also known in the art as an USART module. Such an interface module informs the microcomputer or microprocessor connected thereto when it can receive new parallel signal or characters for transmission or can transmit such a character or parallel signal to the microcomputer or microprocessor. With the assistance of a microcomputer or microprocessor, binary signals can, in fact, be processed in this manner, these binary signals being supplied or forwarded via a plurality of lines designed for serial signal transmission. What is thereby disadvantageous, however, is that the expense connected with offering such interface modules is relatively high. In addition, the costs of such interface modules are on the order of magnitude of that of the microprocessors.